High Speed Vision System


High Speed Vision System aims to design and build a prototype vision system for use in RoboCup. The design is will be implemented in an FPGA (Field Programmable Gate Array). A processing speed of 30 frames per second should be achievable.


6 August, 2007
Mani has found some time to work on the project. She's been working with a new pipeline structure. Mani has also been investigating the use of colour spaces as well.
8 May, 2007
Nathan has been working on a structured design for a sorting system. Have a look in the Subversion repository for the VHDL files. A top-level diagram is available here.
27 October, 2006
Today marks the end of the student engineering project. The report and log books have been submitted for assessment. On Tuesday, the project was demonstrated at the final year electrical engineering project exhibition, Endeavour. The project received the award for "Best Research Project".
11 October, 2006
Have confirmed thresholding and smoothing work on the FPGA. Labelling is almost correct too. Have been using the internal RAM blocks in the FPGA to test the processing components. However there are only 65536 bytes available for use. Trying to use the DDR RAM, but is currently reading duplicate data values.
2 September, 2006
An interface to PC via serial port has been made and verified on the development board. The input synchronisation is better, but storage problems have not been resolved yet.
14 August, 2006
Progress has been slow. Some synchronisation issues have been causing issues with reading or writing to memory. Blanking sequences 80h 10h 80h 10h ... have been read from memory as 80h 10h 10h 80h 10h 80h 80h ... Currently redesigning the interface between video input and DDR RAM.
31 July, 2006
The DDR RAM has been successfully written to and read from. Currently working on a more elaborate interface. Hopefully can store a whole frame this week and analyse the data.
17 July, 2006
A simple output interface to two 7-segment displays has been made, which was used to confirm that the video decoder correctly outputs start and end active video codes in the form: FFh 00h 00h XYh. The next step is to get the DDR RAM interface working.
8 July, 2006

The external power supply is unable to supply a stable 3.3V to the Stratix development board. In the next PCB version we will use the 12V supply with a regulator to give a stable 3.3V. There will also be a jumper to allow an external input. I2C headers will also be provided for external testing.

Currently the PCB has been modified to allow an external 3.3V power supply to drive the daughterboard. This should be sufficient until a new PCB has been made.

Work has been done on writing VHDL for the image processing. Interfacing between the FPGA and the PCB is yet to be done, as is the interface to the on-board DDR RAM.

1 July, 2006
PCB completed yesterday. Now working on a parallel port interface to help test our design.
29 June, 2006
PCBs have arrived. We have now started soldering.
27 June, 2006
New website launched.